Automated Micro-architectural Test Generation for Validation of Modern Processors

Design complexity of todays microprocessors is increasing at an alarming rate to cope up with the required performance improvement by adopting complicated micro-architectural features such as deep pipelines, dynamic scheduling, out-oforder and superscalar execution, and dynamic speculation. Since verification complexity is directly proportional to the design complexity, considerable amount of time and resources are spent on design validation. In the current industrial practice, billions of random test programs generated at instruction set architecture (ISA) level are used during simulation-based validation. However, architectural test generation techniques have limitations in terms of exercising intricate micro-architectural artifacts. Therefore, it is necessary to use micro-architectural details during test generation. Furthermore, there is a lack of automated techniques for directed test generation targeting micro-architectural faults. To address these challenges, we present a directed test generation technique at micro-architectural level for functional validation of microprocessors. A processor model is described in a temporal specification language at micro-architecture level. The desired behaviors of micro-architecture mechanisms are expressed as temporal logic properties. We use decompositional model checking for systematic test generation. Our experiments using a processor based on the Power Architecture Technology shows very promising results in terms of test generation time as well as test program length.